1. Field of the Invention
The present invention relates to a sample chuck for wafers and method of testing wafers mounted on the sample chuck.
2. Description of Related Art
Semiconductor wafers are thin, circular slices of doped silicon from which integrated circuits or semiconductor devices are built. Depending on the state of production, the wafers may be referred to as blank wafers, polished wafers, patterned wafers, product wafers, or the like. The largest wafer in current use is 300 mm (12 inch) diameter.
At each stage in the integrated circuit manufacturing process, wafers must be carefully inspected for electrical properties that may have values varying over the surface of the wafers. In a typical apparatus for inspecting the electrical properties of a semiconductor wafer, the wafer is supported on a sample chuck or fixture and a probe tip is caused to contact the surface of the semiconductor. A capacitance-voltage (CV), current-voltage (IV), conductance-voltage (GV), or capacitance-time (Ct) type electrical stimulus is applied to the wafer. The response of the wafer to the electrical stimulus is measured and, from the response, at least one property of the wafer at the point of the probe tip contact is determined.
Prior art sample chucks have flat surfaces for supporting the wafer during testing. They are machined from metals such as aluminum or stainless steel, for example. Sample chucks made from these metals are suitable because they are electrically conductive, providing a uniform potential or electrical ground under the entire wafer during testing. Unfortunately, the wafers can be contaminated by contact with these surfaces. Sample chucks have also been made from pure silicon, but to do so is prohibitively expensive. It has been proposed to manufacture the sample chucks from a conductive metal with a top layer of semiconductor over the surface of the metal so that the semiconductor wafer being tested cannot be contaminated by contact with the conductive metal surface. See application Ser. No. 10/139,685, filed May 3, 2002, entitled “Sample Chuck with Compound Construction”, assigned to a common assignee. The disclosure of that application is incorporated herein by reference.
A sample chuck having a semiconductor top layer for testing a semiconductor wafer has potential benefits over known metallic sample chucks in the areas of flatness and lack of contamination. One potential drawback to such a sample chuck, however, is that under certain circumstances, variations in the semiconductor top layer may present themselves as variations in the measurement of capacitance-voltage (CV) data, for example. These variations in CV derived data for a semiconductor wafer under test might include variations from the underlying metal semiconductor chuck. One such variation might be changes in the “series resistance” as a function of position due, in part, to variations in resistivity of the semiconductor top layer.
Sample chucks, also known as wafer carriers, are manufactured to industry specifications to accommodate the standard wafer sizes and orientation features, such as flats and notches. A typical technique for holding the wafer on the sample chuck is to draw a vacuum on the underside of the wafer as shown, for example, in U.S. Pat. No. 3,811,182 entitled “Object Handling Fixture, System, and Process.” Techniques for overcoming fixture induced measuring errors are disclosed in U.S. Pat. No. 4,750,141 entitled “Method and Apparatus for Separating Fixture-Induced Error From Measured Object Characteristics and for Compensating the Measured Object Characteristic With the Error, and a Bow/Warp Station Implementing Same.”